Increase in wiring delay in metal wiring with miniaturized multi-layered LSI and 3D memory is a large problem. In order to decrease the wiring delay, it is important to decrease wiring resistance and interwire capacitance. Application of a low-resistance material such as Cu, for example, is put into practical use for decreasing the wiring resistance. Unfortunately, Cu wiring also has problems such as stress-migration- or electromigration-induced degradation of reliability, a size effect-induced increase in electric resistivity, and embedding into fine via holes, and there has been a demand for wiring materials with lower resistance and higher current density tolerance.
Application of a carbon-based material such as a carbon nanotube and a graphene with an excellent physical property such as high current density tolerance, electric conduction property, thermal conductivity, and mechanical strength attracts attention as a next-generation wiring material expected to be low-resistance and highly reliable material. Especially, there have been studied wiring structures having lateral interlayer wiring formed using graphene. A method for forming a graphene wiring includes uniformly forming a graphene film on a substrate and patterning the graphene film into a wiring form or growing graphene on a catalyst layer that has been formed in a wiring pattern.
However, if a graphene wiring is made as thin as about 10 nm, the wiring may be turned into a semiconductor due to the quantum confinement effect of electrons, or the resistance of the wiring may increase due to the scattering effect at the edge.